VLSI : Making of the Super-chip

Realizing the increasing pressures of data processing on equipments
innovation in the architecture of chips to increase the speed of data processing
is the obvious offshoot. Whether it is System-on-Chip or Application Specific
Integrated Circuits (ASIC), the final objective is to have better computing
ability for devices and equipment. This, combined with the fact that consumers
want mobility in devices, is driving innovations to cut down the size of
processors.

VLSI companies have come up with chips that have a maximum of four CPU cores
at present. Four core mobile handsets are in the development stage. In the next
couple of years handsets with multi-core processors will dominate the market.

For the time being, manufacturers are using multiple chips to support
features in the hand phone. In the coming times, all chips will be integrated in
a single chip because using multicore chips handset is likely to deliver better
performance with high energy efficiency. In handsets, frequency on the
processors can be raised but the power available will not be able to support it
for a long period. The fastest processor available in the mobile phone has a
frequency of 800 MHz and by the year end the market can get to see mobile phones
with processor frequency of over 1 GHz.

The VLSI chip developers are focusing on developing chips that can address
various technology protocols like GSM, CDMA, 3G, 4G, WiMax and LTE. If a handset
compatible with all these technologies is to be built, it might be of an old
military wireless handset size. Hence, there is the pressure on scientists to
develop a chip that can support upcoming technologies, taking care of the size
and power limitations of handsets.

Realizing the various limitations in the VLSI space, companies are now
looking at software defined radio. SDR will have common circuitry at the bottom
and software will fulfill the demand of basis features that customers want. SDR
as a technology has been in existence for the last four-five years but it is not
a practical option for handset manufacturers. In order to do the kind of
programming required to drive the circuit there is the need of a hardware to
support it. After the 32 nm chips, manufacturers are rethinking on SDR based
technologies.

New Architectures

The quest of VLSI chip developers is to develop energy efficient small size
chips and chipsets with high performance. Performance of new innovative
technologies is discussed in terms of giga, tera and petaflops.

Pipeline architecture that connects various components in System-on-Chip and
occupies space is the other worry. As an alternative to the multi-core
architecture, there is an EDGE architecture on which tremendous amount of work
is being done. Scientists are also developing 130 nm TRIPS (Tera-op, Reliable,
Intelligently adaptive Processing System) chip.

Before EDGE Instruction Set Architecture (ISA), it was reduced instruction
set computing architecture (RISC) which was used in x86 and its equivalent. RISC
architecture worked on register-to-register architecture and attained high
performance with the help of aggressive pipelining and careful compiler. Intel
scaled its x86 line more than 100 folds from 33 MHz to 3.4 GHz in around 14
years.

Experts panel

Sreedhar Venkatraman, director, Solutions and Services, Nortel Pantulu Avasarala, CEO, Cincom Ganesh Guruswamy, VP and director, Freescale Semiconductor India Ramesh Kumar, director, Asia, infrastructure DSP, Texas Instruments CS Rao, MD, South Asia & Middle East, Intel Anil Gupta, MD, ARM Embedded Technologies Steve Keckler, professor, department of computer science, University of Texas

Available Chips

In the telecom space, devices at are using a maximum of six core DSPs. On the
handset side upgrading the chips alone and retaining the old devices is
generally not possible. The chipset forms only a component in a range of
functions in the wireless device. In addition to the chipset, associated
circuitry, software stack, user interface and interactivity for the newer
services, etc, would all have to change. So if a user has a 2G phone with only
GSM voice capability, or a 2.5G phone with GSM and GPRS/EDGE capabilities, does
not mean that they will be able to use 3G services or upgrade their devices to
3G services. They would need to buy a new device that supports 3G.

Gradually, SoCs/ASICs which are at research level, will make their way into
devices to cater to the technology needs of consumers. At present we see chips
that only process data but in the future we may expect to see chips that will
adapt as per the needs of devices.

Scalability and Parallelism

Scientists today are aiming to make a brain-like processor. The human brain
is one of the most complex and fastest supercomputer that has the ability to
process multiple messages at one go.

The scientists who are involved in the making of miniature processors are
emphasizing on processing multiple instructions, data and thread at one go with
the help of parallelism and compilers. Simultaneously, scalability also counts.
These miniature chips have been provided by a network router.

The prototype TRIPS chip can be scaled up to 32 chip system without any
fundamental limitation. This will not only help in easy communications between
cores but also easy clustering for to attain enhanced performance.

But to take advantage of this level of processing speed, there is a problem
at the software level. In case of multicore chips, there arises a question on
the way the work should be sub-divided which needs to be done by user
applications. The cores available on the dye are just like additional resources.

The programming methodology are tuned, at most, to Intel's quad core. The
fact is that today there is no system that works on 80 core microprocessors.
Hence, there is a need to change programming methodology and find ways to
exploit parallelism in applications necessary to achieve true supercomputer
performance. Once that happens performance will reach a level beyond
imagination.

There is still a gap which has to be filled by finding new ways of putting
program together and allocating memory to application. On the processor front,
the next task remains to provide individual processing elements that provide
substantial performance advantages so that programmers need not explicitly
parallelize their programs but do it in the most efficient way possible.

Prasoon Srivastava

prasoons@cybermedia.co.in